14 Channel Configurable PMIC Evaluation Board
Created: Jul 24, 2015
No description available.
This circuit design allows full evaluation capability of the PF0100 SMARTMOS Power Management Integrated Circuit (PMIC) for the i.MX6 family of application processors. The PF0100 provides a highly programmable/ configurable architecture, with fully integrated power devices and minimal external components. With on-chip One Time Programmable (OTP) memory, the PF0100 is available in preprogrammed standard versions, or non-programmed to support custom programming. The PF0100 is defined to power an entire embedded MCU platform solution such as i.MX6 based eReader, IPTV, medical monitoring, and home/factory automation.
The board provides access to all output voltage rails as well as control and signal pins through terminal block connectors. A single terminal block connector for the input power supply allows the user to supply the board with an external DC power supply to fully evaluate the performance of the device. The board comes with a non-programmed version of the PF0100 PMIC, so it is prepared to power up from the default sequence. However, an integrated control programming interface is provided to allow the user to program the OTP/TBB (One Time Programmable / Try-Before-Buy) memory and also to select it as the default source for the power-up configuration. Likewise, the programming interface allows full control of the PF0100 through the I2C communication lines.
The board operates with a single power supply from 3.1 V to 4.5 V and is controlled via USB with help of an integrated USB-I2C communication bridge. By applying the input voltage supply, the board powers up according to the default power-up sequence.The PF0100 can provide power for a complete system, including applications processors, memory and system peripherals in a wide range of applications with up to six buck converters, boost regulator to 5V output , six general purpose linear regulators, coin-cell charger and RTC supply, and power control logic with processor interface and event detection.