14 Channel Configurable Power Management Integrated Circuit
Created: Jan 07, 2016
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This reference design is a typical application circuit of the PF0100 Power Management Integrated Circuit (PMIC) together with its practical components. The PF0100 PMIC provides a highly programmable configurable architecture, with fully integrated power devices and minimal external components. It features four buck regulators (up to six independent outputs), one boost regulator, six general purpose LDOs, one switch/LDO combination and a DDR voltage reference to supply voltages for the application processor and peripheral devices. The default PF0100 power-up sequence is programmed to fit the requirements of the i.MX 6 series families of processors. However, the PF0100 can be adjusted to meet the specific requirements for system applications by using the one time programmable (OTP) feature.
The number of independent buck regulator outputs can be configured from four to six, thereby providing flexibility to operate with higher current capability, or to operate as independent outputs for applications requiring more voltage rails with lower current demands. Further, SW1 and SW3 regulators can be configured as single/dual phase and/or independent converters. One of the buck regulators, SW4, can also operate as a tracking regulator when used for memory termination. The buck regulators provide the supply to processor cores and to other low voltage circuits such as IO and memory. Dynamic voltage scaling is provided to allow controlled supply rail adjustments for the processor cores and/or other circuitry. Depending on the system power path configuration, the six general purpose LDO regulators can be directly supplied from the main input supply or from the switching regulators to power peripherals, such as audio, camera, Bluetooth, Wireless LAN, etc. A specific VREFDDR voltage reference is included to provide accurate reference voltage for DDR memories operating with or without VTT termination. The VSNVS block behaves as an LDO, or as a bypass switch to supply the SNVS/SRTC circuitry on the i.MX processors; VSNVS may be powered from VIN, or from a coin cell.
The PF0100 PMIC is fully programmable via the I2C interface. Additional communication is provided by direct logic interfacing including interrupt and reset. Start-up sequence of the device is selected upon the initial OTP configuration, or by configuring the “Try Before Buy” feature to test different power up sequences before choosing the final OTP configuration. The PF0100 PMIC has the interfaces for the power buttons and dedicated signaling interfacing with the processor. It also ensures supply of critical internal logic and other circuits from the coin cell in case of brief interruptions from the main battery. And a charger for the coin cell is included as well.
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