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 NXP Semiconductors

  • 16-bit I2C and SMBus Low Power I/O Port

  • Created: Jan 30, 2014

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This designed circuit is a System Management Bus (SMBus), which is a single-ended simple two-wire bus for the purpose of lightweight communication. Most commonly, it is found in computer motherboards for communication with the power source for ON/OFF instructions. It is derived from I²C for communication with low-bandwidth devices on a motherboard, especially power related chips such as a laptop's rechargeable battery subsystem. Other devices might include temperature, fan or voltage sensors, lid switches and clock chips. PCI add-in cards may connect to an SMBus segment. While I²C is a multimaster serial single-ended computer bus invented by the Philips semiconductor division, today NXP Semiconductors, and used for attaching low-speed peripherals to a motherboard, embedded system, cellphone, or other digital electronic devices.

The PCA9535 is a 24-pin CMOS device that provides 16 bits of General Purpose parallel Input/Output (GPIO) expansion for I2C-bus/SMBus applications and was developed to enhance the NXP Semiconductors family of I2C-bus Input/Output (I/O) expanders. The improvements include higher drive capability, 5 V I/O tolerance, lower supply current, individual I/O configuration, and smaller packaging. I/O expanders provide a simple solution when additional I/O is needed for Advanced Configuration and Power Interface (ACPI) power switches, sensors, push buttons, LEDs, fans, etc. The PCA9535 consists of two 8-bit configuration (I/O selection), input, output and polarity inversion (active HIGH or active LOW operation) registers. The system master can enable the I/Os as either inputs or outputs by writing to the I/O configuration bits. The data for each input or output is kept in the corresponding I/O register. The polarity of the read register can be inverted with the polarity inversion register.

The number of data bytes transferred between the START/STOP conditions from transmitter to receiver is not limited. Each byte of eight bits is followed by one acknowledge bit. The acknowledge bit is a HIGH level input on the bus by the transmitter, whereas the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate acknowledge after the reception of each byte. A master must also generate acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that confirms the transmission has to pull down the SDA line during the “acknowledge” clock pulse, so that the SDA line is stable LOW during the HIGH period of “acknowledge” related clock pulse. A master receiver must signal an end of data to the transmitter by not generating “acknowledge” on the last byte that has been clocked out of the slave.