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  • 5P49V5935 - VersaClock 5 Programmable Clock Generator with Integrated Crystal

  • Created: Nov 13, 2017

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Description

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Summary

This reference design features the use of 5P49V5935 programmable clock generator that is well suited for networking and data communications applications. It is the fifth generation of programmable clock technology that has an integrated 25MHz crystal as input reference. It allows up to 4 different configurations to be programmed which is accessible using processor GPIOs or bootstrapping. The different selections may be used for different operating modes.


The 5P49V5935 supports an internal One-Time Programmable (OTP) memory that can be pre-programmed with up to 4 complete device configurations. These configurations can be over-written using the serial interface once reset is complete. Any configuration written via the programming interface needs to be re-written after any power cycle or reset. This clock generator has an input clock select that basically selects the active input reference source in manual switchover mode. It also has a redundant external clock input. The primary clock designation which is the main reference clock to the PLL while the non-primary clock is designated as the secondary clock in case the primary clock goes absent and a backup is needed. The primary and secondary clock source setting is determined by the PRIMSRC bit. Moreover, the OUT1 to OUT4 clock outputs are provided with register-controlled output drivers. By selecting the output drive type in the appropriate register, any of these outputs can support LVCMOS, LVPECL, HCSL or LVDS logic levels. The VDDO pins have different output voltage levels where the output voltage levels of 2.5V or 3.3V are supported for differential HCSL, LVPECL operation, and 1.8V, 2.5V, or 3.3V are supported for LVCMOS and differential LVDS operation. Each output may be enabled or disabled by register bits or logic 1 or 0 state.



With its promising capabilities, the 5P49V5935 programmable clock generator featuring its programmable loop bandwidth, slew rate control and output to output skew is efficient for high performance consumer, industrial and computing applications. In I2C mode operation, the device acts as a slave device on the I2C bus using one of the two I2C addresses allowing multiple devices to be used in the system.