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 NXP Semiconductors


  • Bidirectional Translation for Higher Voltage Levels

  • Created: Sep 08, 2014

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Summary

Advances in assembling techniques in the creation of semiconductors have taken into account for smaller geometries in circuit design and lower supply voltage levels. These advances in technology help a large portion of the low-power, high-performance applications presently being planned. To utilize these new plans with existing technology, there must be a means to match the output voltage level of one device with the input voltage level of an alternate device in the circuit. The diverse technologies accessible in circuit design determine the input voltage threshold and output voltage level achievable in different devices. To interface two devices of differing technologies successfully, voltage level translation may be required. These requirements include: The high-level output voltage (VOH) of the driver device must be greater than the high-level input voltage (VIH) of the receiver device, the low-level output voltage (VOL) of the driver device must be less than the low-level input voltage (VIL) of the receiver and the output voltage from the driver must not exceed the I/O voltage tolerance of the receiver.


The circuit uses a NVT2008/NVT2010 bidirectional voltage level translators operational from 1V to 3.6V Vref(A) and 1.8V to 5.5V Vref(B), which allow bidirectional voltage translations between 1V and 5V without the need for a direction pin in open-drain or push-pull applications. The bit widths of 8-bit to 10-bit are offered for level translation application with transmission speeds < 33MHz for an open-drain system with a 50pF capacitance and a pull-up of 197Ω.


In addition NVT2008/10 can be used in level translation applications for interfacing devices or systems operating at different interface voltages with one another. The NVT2008/10 is ideal for use in applications where an open-drain driver is connected to the data I/Os. The NVT2008/10 can also be used in applications where a push-pull driver is connected to the data I/Os.

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