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 NXP Semiconductors


  • EEPROM DIP Switch with Jumperless Configuration

  • Created: Oct 08, 2014

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Summary

This generic design of I2C interface features 6-bit 5-to-1 multiplexer DIP Switch and four internal non-volatile registers in which it increases the interface performance between CPUs, chipsets, and protocol controllers. It is advantageous for speed step configuration that allows dynamic change of clock speed. It also boosts performance of CPU up to 7.5% with lower power consumption.


The design is comprised of PCA9561PW Quad 6-bit multiplexed I2C EEPROM DIP switch, which is used for Voltage IDentification code or VID configuration. It bypasses the defined VID values and provides a different set of VID values to the Voltage Regulator Module or VRM that meets the desired CPU voltage. This achievement of desired CPU voltage and clock speed leads to an increase in CPU performance. The DIP switch connected to WP pin is used as write protect switch. In this design part, the CPU serves as the receiver of data generated by chipsets and protocol controllers. These chipsets and protocol controllers are subcomponents that manage data flow from memories, peripherals, computer networks, and other related digital system to be interfaced with the CPU.


The significance of having better CPU performance is that the system operation will be optimized. The energy of the device will last longer, since optimized system means low power consumption and heat generation. Without the need of powering down equipment for some changes in its settings is already a great advantage to servers and networking applications. It will not interrupt any valuable data transfer.

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