Created: Aug 28, 2014
No description available.
This designed circuit protects messages from being jammed. The scrambling is an operation carried out in the analog domain. It makes the message unintelligible at a receiver not equipped with appropriate set of descrambling circuit.
The design is composed of different logic components. The TP3054 is an Enhanced Serial Interface CODEC/Filter that is used for high-pass and low-pass filtering transmission, receive low-pass filter with sin x/x correction, active RC noise filters, m-law or A-law compatible COder and DECoder, internal precision voltage reference, serial I/O interface and internal auto-zero circuitry. The 74HC74D is a dual positive edge triggered D-type flip-flop that makes the circuit highly tolerant to slower clock rise and fall times. The 74LVC161 is a synchronous presettable binary counter that has an internal look-ahead carry and it can be used for high-speed counting. The 74HC7266DB is a high-speed Si-gate CMOS device and it is pin compatible with low power Schottky TTL(LSTTL). The entire system accomplishes the frequency-inversion algorithm via digitization of the audio, inversion of the sign of every algorithm via digitization of the audio, inversion of the sign of every alternate sample, and D/A conversion of the resultant data. The result is an inverted frequency spectrum.
It is best suited to electronic system and technologies where communication system is widely used. It provide additional security of signals while they are in the transmission line.