32 kHz watch circuits with EEPROM
Created: Sep 08, 2014
No description available.
In a watch circuit, power utilization is basic in light of the fact that battery life and battery size are identified with the power utilization of the circuit. For the most part, the less power needed, the littler the permissible battery size and the more extended a battery of a given size will last. Watch circuits ordinarily incorporate an oscillator for delivering intermittent pulses at a stable frequency, and a chain of frequency divider stages for separating the oscillator frequency down to a convenient periodic time reference, for example, one pulse every second. The one pulse every second signal drives timekeeping circuitry, which gives signal to the watch display. Since the oscillator and the first few divider phases of the frequency divider chain work at the most astounding frequency of the circuit, a significant rate of the aggregate circuit power utilization happens there.
The PCA1462U series devices are CMOS integrated circuits specially suited for battery-operated, quartz-crystal-controlled wristwatches, with bipolar stepping motors.
The power consumption of the oscillator can be reduced by reducing the gain of the amplifier used in the regenerative feedback loop of the oscillator. However, if the oscillator amplifier gain is reduced so that a significant reduction in operating current is realized, then the time required for the oscillator to start when battery power is initially applied to the circuit becomes excessively long, or the oscillator may fail to start at all. Since the starting time of the oscillator is partially dependent on external capacitors used for trimming the oscillator frequency, the starting time, or the failure to start, varies with each individual watch circuit. Preferably, the starting time should be no longer than 3 seconds in order to expedite testing of watch assemblies during manufacture, and to be acceptable to the consumer.