Analog Front-End Reference Design for Imaging Using Time-Interleaved SAR ADCs with 73dB SNR, 7.5MSPS
Created: May 23, 2018
This reference design demonstrates how to achieve multiple ADC interleaving with high sampling rates and good resolution at low BOM-cost. The reference design was built with electronic imaging systems in mind. High definition imaging and other high speed signal processing applications require ADCs that can achieve high resolution, high SNR, high speed and low power consumption. These requirements cannot always be met with a single chip. By interleaving multiple SAR ADCs, the design optimizes trade-offs between different ADCs in order to meet all of the system requirements.
The TIDA-01355 design presents an alternate solution to this problem. Instead of flash or pipeline ADC architectures, this TI Design uses time-interleaved SAR ADCs. This reference design takes electronic imaging systems as an example to demonstrate how to implement interleaving using multiple low-power SAR ADCs to achieve higher sampling rates at a reasonably high resolution and low cost. Time interleaving provides clear advantages in terms of power and speed. However, these advantages do not come for free. Mismatches among multiple paths of the signal chain result in substantial spurious content in the output spectrum. Correcting unwanted interleaving spurs might come at a heavy cost in terms of complexity and power. Understanding which errors are most significant and which can be ignored in any given application is important for selecting an appropriate calibration scheme.