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  • Simple Timer Circuit Using Binary Counter

  • Created: Nov 18, 2014

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This timer circuit is a simple alarm system that can be easily constructed by electronic enthusiasts. It uses 74HCT4060D binary counter, a 14 stage ripple carry counter/dividers which is a high speed SI gate CMOS device. It has three oscillator terminals (RS, RTC and CTC), ten buffered outputs (Q3 to Q9 and Q11 to Q13) and an overriding asynchronous master reset (MR). The oscillator configuration allows design of either RC or crystal oscillator circuits. The oscillator may be replaced by an external clock signal at input RS.

The IC has a built-in oscillator that needs just a few passive external components for it to tick. Oscillation periods can be varied right from a few fractions of a second to many hours that depends solely upon the values of the external RC components. RC components refer to the values of the external time, determining components consisting of a resistor or a potentiometer and a capacitor. The outputs produce a varied rate of time periods where each output generates time periods that is exactly double to that of the previous output in a certain order of the IC pin outs. The advantage of constructing a timer using IC 74HCT4060D is its timing capacitor is kept small as possible and only the resistor will be essentially adjusted to a higher value. This helps keep the circuit simple, smaller and very sleek. In, addition, the diode in the circuit acts as a latching component, which latches the IC once the set time lapses and the output of the IC goes high. Moreover, the buzzer is an indication if the time delay has elapsed. The IC may be reset simply by pressing the reset button or alternatively the circuit gets automatically reset when switched off and powered again.

The simplicity of the design will be helpful for beginner electronic enthusiasts in constructing a fixed timing device. The time delay can be varied through RC, which may take hours to alarm. This device may be integrated to any electronic device that needs a fixed timing system to optimize its performance.