Typical LVPECL Output Termination
Created: Jul 02, 2015
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The Low Voltage Positive Emitter Coupled Logic (LVPECL) is an established high frequency differential signaling standard. It is an enhanced version of Positive Emitter Coupled Logic (PECL), a differential signaling systems that is usually used in high speed and clock distribution circuits. The ICS853S01I is a high performance differential-to-LVPECL multiplexer. It can also perform differential translation because the differential inputs accept LVPECL, LVDS and CML levels. The ICS853S01I is packaged in a small 3mm x 3mm 16 VFQFN package, making it ideal for use on space-constrained boards.
The clock layout topology shown in the circuit is a typical termination for LVPECL outputs. The two different layouts illustrated are recommended only as guidelines. The differential output pair is low impedance follower output that generates ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50Ω transmission lines. The matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations.
The typical applications of LVPECL are high-speed video, graphics, video camera data transfers, and general-purpose computer buses. It has become popular in products such as LCD-TVs, automotive infotainment systems, industrial cameras and machine vision, notebook and tablet computers, and communications systems.